1. Field of the Invention
The present invention relates to semiconductor memory devices. More particularly, the invention relates to a sense amplifier circuit having a self-reference and capable of being incorporated with a flash memory device, as well as a related sensing method.
This application claims priority under 35 U.S.C. §119 to Korean Patent Application 10-2006-0108305, filed on Nov. 3, 2006, the subject matter of which is hereby incorporated by reference in its entirety.
2. Discussion of Related Art
Semiconductor memory devices, such as Dynamic Random Access Memory (DRAM), Static Random Access Memory (SRAM), flash memory, etc., all operate according to certain basic operations, nominally referred to as read and write operations. The approaches to writing data in these different memories vary widely. The approaches to reading data from the different memories also vary in many respects. However, most read operations make use of a specialized output circuits which may be generically said to perform functions associated with a sense amplifier circuit.
In particular, flash memory devices use a sense amplifier circuit operate in read, program, verify, and erase verify operations. A constituent sense amplifier circuit (or sense amplifier like circuit) is implicated in many, if not all, of these operations. Conventional flash memory devices often incorporate a sense amplifier functionality in sense circuits implemented using a current mirror, (e.g., a differential sense amplifier), or a single ended sense amplifier. Despite their widespread use, however, conventional sense amplifier circuits suffer from several notable problems.
Figure (FIG.) 1 is a block diagram generally illustrating a conventional sense amplifier. Referring to FIG. 1, a sense amplifier circuit S/A 10 is connected between a reference voltage generator 12 and a memory cell 14.
Sense amplifier circuit 10 is a current mirror type circuit in which a bit line voltage BL is compared with a reference voltage Vref during read and verify operations. During this voltage comparison, current flows to a transistor in the current mirror circuit having a relatively high voltage. In accordance with the comparison, sense amplifier circuit 10 provides a differential output signal (Vout, /Vout). This type of current mirror sense amplifier circuit is conventionally well understood.
As commonly implemented, reference voltage generator 12 is separately provided on a different part of the constituent substrate from the memory cell array containing memory cell 14.
Memory cell 14 is a flash memory cell in the assumed example. In order to obtain sense and amplification operation through sense amplifier circuit 10, a word line coupled to the gate of memory cell 14 must first be selected, and a bit line associated with the drain or source of memory cell 14 must also be selected.
FIG. 2 is a block diagram illustrating another conventional example of a sense amplifier. This conventional embodiment includes a sense amplifier circuit 20, a dummy cell 22, and a memory cell 24. In comparison with FIG. 1, dummy cell 22 of FIG. 2 is added to generate a reference voltage Vref required by sense amplifier circuit 20.
Dummy cell 22 is commonly disposed in a region of the substrate on which sense amplifier circuit 20 is constructed which is different from the region in which memory cell 24 is disposed.
Whether a reference voltage generator or a dummy cell is implemented, the overall size of the conventional flash memory device is unfortunately large. The separate provision (i.e., location at different portions of the underlying substrate) of the reference voltage source is one cause for this size issue.
Further, errors in the operation of the flash memory device may result from ineffective electrical connections between bit lines and the peripherally located circuits generating the reference voltage.
Furthermore, various process related variables may result in differences in the endurances and/or threshold voltages Vt between the main memory cells and associated dummy cells. Such differences may result in reference voltage producing dummy cells that have low current driving capabilities relative to the main memory cells.